Computing devices are ubiquitous in our daily lives. Personal computers are good examples as they are used in a variety of daily activities from routine word processing tasks to running complex mission-critical business applications. The use of peripheral input and output (I/O) devices has considerably expanded the usefulness of PCs. Printing documents, sharing storage media and other resources across a network, recording audio, playing music and streaming video are now all fairly common activities that take place on the PC. This has been made possible by the use of graphics cards, sound cards, and network interface cards that are added to the PC by way of expansion slots.
Not surprisingly, peripheral devices constitute a major subsystem of the modern PC. Modern PC architectures include a processing subsystem, peripheral interface circuits and peripheral devices. The processing subsystem includes one or more processors, system memory, and devices with low-latency requirements such as graphics cards, which often require privileged access to system memory. The peripheral interface circuits act as a bridge allowing peripheral devices to communicate with the processing subsystem.
The peripheral interface circuits typically support several interface buses to communicate with peripheral devices, added by way of expansion slots. In a typical architecture, peripheral interface circuits can be further subdivided into a high speed bus interface (often referred to as a “north-bridge” or “root complex”) that interfaces with the processor, memory and graphics; and an I/O interface (often referred to as a “south-bridge”) that communicates with lower speed peripheral I/O devices using a variety of peripheral buses.
To allow interoperability of peripheral devices, peripheral busses adhere to agreed-upon standards that define the physical and logical requirements of any interface and bus used to connect the peripherals. Over time, many such peripheral bus standards have been devised. These include ISA, EISA, PCI (Peripheral Component Interconnect), PCI-X, and the AGP bus. Each new standard strives to address bandwidth limitations of earlier standards.
The recently introduced PCI Express (PCIe) bus offers a higher bi-directional bandwidth to meet the demands of modern peripherals, such as graphics adapters operable to present real-time video, and 3D graphics. The PCIe standard is detailed in “PCI Express Base Specification. Revision 1.0a” which is available through the PCI Special Interest Group (PCI SIG) and is hereby incorporated by reference.
A particularly useful feature of the PCIe bus is the ability of peripheral devices added by way of an expansion slot to utilize some or all of the available data lines extending to an interface slot. That is, unlike earlier bus standards, such as the PCI bus, where a single fixed width bus was shared by all devices, the PCIe standard defines point to point links between devices in a scalable manner. The PCIe standard defines links consisting of 1, 2, 4, 8, 12, 16 or 32 logical data lines called lanes. A link that is made up of a single data line or lane is called a x1 link; a link with two lanes is a x2 link, and so on. A PCIe device that is capable of using 8 data lines is called x8 capable. The same device may be x1 capable, x2 capable, x4 capable and x8 capable. All devices are required to be x1 capable.
However, because links are point to point and data lines are not shared among expansion slots, unused lanes to any peripheral expansion slot or device typically cannot be used by other devices interconnected with the bus.
Accordingly, there is a need for an improved design that more flexibly allows bus bandwidth sharing among peripheral devices.